前端数字设计工程师
主要工作与职责：
参与芯片前端数字模块的设计开发，仿真，验证以及综合工作。
职位要求：
微电子等相关专业本科或本科以上学历，良好的英文读，写能力。
3年以上基于Verilog 和 RTL的芯片设计经验。
熟悉数字电路设计流程，能独立完成模块设计。
独立完成电路仿真测试计划及代码开发。
有DC综合, STA静态时序分析, P&R自动布局布线等经验优先。
能熟练使用Verilog XL, ModelSim, NC-Verilog, and VCS 。
熟悉UNIX 环境和Shell 和其它脚本语言如Perl, Tcl。
会使用版本控制和bug tracking工具
低功耗电路设计设计经验
具有积极主动的工作态度，具备良好的分析能力、解决问题能力、沟通能力和优秀的团队协作能力。
Job Description
A Senior Logic Design Engineer involved in the development and delivery of IC frontend behavior models, verification methodologies and memory controllers.
Desired Skills and Experience

Extensive hands on experience on Verilog behavioral and RTL coding techniques and synthesis
Experience in developing standard EDA views such as Verilog and Liberty
Experience in testbench and testplan development of semiconductor memories
Experience in working with logic simulators like Verilog XL, ModelSim, NC-Verilog, and VCS
Strong knowledge of UNIX environment, shell scripting and scripting languages such as Perl/Tcl
Experience in using revision control and bug tracking tools.
Working knowledge of low power verification using CPF/UPF is a plus
Excellent communication and problem solving skills
Ability to work well as part of a team across different functional groups